1. Field of the Invention
The present invention relates to an automatic frequency control (AFC) circuit suitable for obtaining a low-frequency converted color subcarrier signal phase locked at a horizontal sync signal of a television signal of a video tape recorder (VTR), for example.
2. Description of the Related Art
In general VTRs, a color subcarrier signal is converted into a signal of low frequency before its recording. An AFC circuit is used for obtaining a color subcarrier signal exactly synchronized with a horizontal sync signal of a television signal. The AFC circuit includes an AFC loop functioning as below. A horizontal sync signal at a frequency f.sub.H of a television signal is phase compared with a signal that is a signal whose frequency is 1/N of a frequency (f.sub.0) of an output signal of a voltage controlled oscillator (VCO), where N is a positive integer. The oscillation of the VCO is controlled on the basis of the result of the phase comparison so that f.sub.0 =Nf.sub.H.
The AFC circuit may be configured by a digital technology as below. It comprises: a sync separation circuit for separating a horizontal sync signal from a composite sync signal supplied to an input terminal; a phase comparator for phase comparing the horizontal sync signal derived from the sync separation circuit with a pulse signal output from the VCO through a logical operation of the horizontal sync signal and the pulse signal; a switch circuit whose connection state is switched in accordance with the result of the phase comparison; a filter whose charge/discharge is controlled by a connection state of the switch circuit; a first constant current source outputting a charging current +I.sub.0 for the filter; a second constant current source for feeding a discharge current -I.sub.0 to the filter; the VCO whose oscillating frequency f.sub.0 is controlled by a voltage across the filter; and a counter for demutiplying a frequency of the output signal of the VCO into a 1/N frequency and supplying it to the phase comparator. The phase comparator has a first AND gate for logically summing the horizontal sync signal derived from the sync separation circuit with the frequency demultiplied signal derived from the counter, and a second AND gate for logically summing the horizontal sync signal derived from the sync separation circuit with a signal that is an inverse of the frequency demultiplied signal derived from the counter.
In the AFC circuit thus configured, the counter demultiplies the frequency of the output pulse signal of the VCO into a frequency of a factor of N, to form a pulse signal of the same frequency as that of the horizontal sync signal. The output signal of the first AND gate, which logically multiplies the frequency demultiplied pulse signal and the horizontal sync signal from the sync separator, is of a nature such that its pulse width becomes wider, the more the phase of the output signal of the counter advances, and it becomes narrower, the more that phase lags. The output signal of the second AND gate has a reverse nature to that of the first AND gate, that is, its pulse width becomes narrower, as the phase of the counter output signal advances, and it becomes wider, as that phase lags.
The output signals of the first and second AND gates control the switch circuit for the charge/discharge and hold operations of the filter. More specifically, when the output signal of the first AND gate has a high logic level, the switch circuit connects the second constant current source to the filter, to allow a discharge of the filter. The result is a decrease in control voltage for the VCO. When the output signal of the second AND gate has a high logic level, the switch circuit connects the first constant current source to the filter, to allow charging of the filter. The result is an increase of the control voltage for the VCO. When the output signals of the first and second AND gates are both low, the switch circuit is in a neutral state, so that the control voltage is held.
In other words, when the trailing edge of the counter output signal is located at the center of the pulse duration of the horizontal sync signal, the pulse width of the output signal of the first AND gate is equal to that of the output signal of the second AND gate. The result is that the charge and discharge times are equal to each other, and the voltages across them are also equal to each other. Under this condition, an oscillating frequency f.sub.0 of the VCO is locked at frequency Nf.sub.H. A subsequent frequency demultiplication of the oscillating signal into a 1/8 frequency produces a low frequency converted color subcarrier signal synchronized with the horizontal sync signal.
The AFC circuit thus arranged changes the ratio of the charge and discharge times of the filter for the pull-in operation. Therefore, even in a locked state of the AFC, a ripple component appears in the control voltage during a phase detect period (charge and discharge periods). More exactly, the AFC is locked so that f.sub.0 =Nf.sub.H is satisfied, where f.sub.0 is an oscillating frequency of the VCO for an average value of the control voltage. For the instantaneous control voltage, the oscillating frequency f.sub.0 of the VCO is not always equal to Nf.sub.H. When the relationship f.sub.0 =Nf.sub.H is not satisfied, a frequency in the vicinity of the burst of the video signal component deviates significantly, leading to a major deviation of hue.
If the filter values are set to appropriate values, the control voltage may be constant in the video signal component, but the relation f.sub.0 =Nf.sub.H cannot be satisfied.
As just mentioned, in the conventional AFC circuit, the control voltage for the VCO contains a ripple component even in the locked state of the AFC. The VCO oscillates so as to satisfy f.sub.0 =Nf.sub.H for the average value of the control voltage. However, this relation does not hold for the instantaneous value. The inequality of those frequencies leads to a great color irregularity. This problem requires an urgent solution.